The present invention relates generally to integrated circuit design and, more particularly, to the design of input/output circuits which can withstand voltages higher than the supply voltages for the integrated circuit.
Integrated circuits typically have input/output (I/O) circuits which act as an interface between the rest of the integrated circuit and the electrical environment external to the integrated circuit. The I/O circuit drives electrical signals generated by the integrated circuit to a pad which is connected to the external environment, or receives signals for the integrated circuit from the external environment through the pad.
A constant drive in integrated circuit technology is toward greater integration with more devices on an integrated circuit substrate. Each successive fabrication technology has demanded smaller geometries and thinner gate oxides in the case of MOS technologies. Due to device breakdown at higher voltages, as well as power considerations, lower power supplies have become increasingly commonplace for integrated circuits. For example, at 0.5 .mu.m and 0.35 .mu.m CMOS technologies, power supplies are typically +3.3 V. However, a problem arises when the integrated circuit must interface with other integrated circuits and systems operating at the older power supply standard, +5.0 V, for example.
FIG. 1 graphically illustrates the problem. In this case, two integrated circuits 10 and 11 both share a bus line 12. The integrated circuit 10, which operates with a +3.3 V power supply, i.e., between 0 and +3.3 volts, has an I/O driver circuit 14 which is connected to a pad 13 and to an input node 16. In response to logic signals from the rest of the integrated circuit 10, the circuit 14 drives the logic signals onto the pad 13 in a voltage range between 0 and +3.3 volts. The pad 13 is connected to the bus line 12 which, in turn, is connected to a similar pad (not shown) on the integrated circuit 11. The integrated circuit 11, which operates at a +5.0 V power supply, i.e., between 0 and +5.0 volts, drives the bus line 12 in a voltage range between 0 and +5.0 volts through an I/O driver circuit 15 in response to logic signals on an input node 17 to the circuit 15. Of course, while the I/O circuit 15 is stated as part of the integrated circuit 11, the circuit 15 might be also a separate device which drives the bus 12. Nonetheless, the problems stated are basically the same.
When the I/O circuit 14 on the integrated circuit 10 is not in operation, the I/O circuit 14 is disabled by an OE (Output Enable) control signal, as shown in FIG. 1. At the same time, the I/O circuit 15 on the integrated circuit 11 is enabled (OE control signal ON, as shown in FIG. 1) to drive logic signals from the integrated circuit 11 onto the bus line 12. The pad 13 receives the logic signals from the I/O circuit 15. Without a proper design of the I/O circuit 14, high discharge currents may pass through the elements of the circuit 14 when the shared bus line 12 is driven to +5 V, i.e., to a voltage greater than I/O circuit's operating voltage. This greater voltage may destroy or degrade the sensitive devices of the I/O circuit 14. Furthermore, the high currents drawn by the circuit 14 might also damage the I/O circuit 15.
Various designs have been proposed to address this problem. However, they all have one or more of the following shortcomings. Some proposed driver circuits may be able to tolerate +5 V, but the output drive of the circuit is too low. Other shortcomings include allowing the N-type bulk regions (the N-well regions holding the PMOS transistors) of the integrated circuit to float with no control during some of the operating conditions. The output drive may be degraded by a badly controlled potential in the N-type bulk regions. Excessive current may flow when the P-diffusion-to-N-well diffusion is forward-biased. High voltages (+5 V) may also be created across the thin gate oxide of the MOS transistors. In some designs the gates of the transistors are connected directly to the pad, which renders the MOS transistors susceptible to undesirable electrostatic discharge.
The present invention avoids, or substantially mitigates, these problems.